1. Field of the Invention
The invention relates to memories and, more particularly, to electrically programmable and electrically erasable non-volatile memories, though it may also apply by extension to other types of memories, either volatile or non-volatile memories.
2. Discussion of the Related Art
The electrically programmable and erasable non-volatile memories, more commonly known as EEPROM memories, are memories currently organized in 1-bit words and not in plural bit words. The reason for that organization is that they are low-capacity memories (a few thousands of bits), often associated with sequential binary information processing circuits. If such memories are used in an application requiring plural bit words, then several parallel memory chips are used, which receive the same addresses and each deliver (or receive) a respective bit of the stored word (or of the word to be stored).
Owing to the technological development in the field of information processing, there is a growing need for higher capacity EEPROM memories (64 kilobits and more). Memories organized in 1-bit words and including a greater number of addresses can still be used. Yet, this gives rise to two types of drawbacks: first, such an organization is somewhat unsuited to the parallel signal processing of plural bit words; and second, regarding the programming is comparatively slow and it is prohibitively time-consuming if not carried out in groups of several bits.
Efforts are therefore devoted to the development of new memories, and especially EEPROM memories, organized in p-bit words (p&gt;1) and with p inputs/outputs to receive words to be stored in a given location or to deliver words stored in that location. One of the problems then encountered is that of reading the stored words. One of the limitations is that of access speed; a stored word is wanted out of the memory as quickly as possible (and of course without this rate giving rise to read errors or to transmission errors in the extracted information). The desired read speed ranges from a few tens to some hundreds of nanoseconds per word. In order to reach such speeds, without running the risk of losing the information to be read, precautionary measures must be taken both for the general organization of the memory cell array and for the read mode.
With regard to the general organization of the array, in rows and columns, it is well known that the rows and columns should preferably not be too long. For example, the access time to a memory cell located at a row end far from the row decoder would be longer (by several tens of nanoseconds for a rather long row) than the access time to a cell located at another row end near the decoder. Additionally, too long columns introduce a high stray column capacitance, which slows down the information read time.
In order to avoid too long columns, measures are therefore taken to distribute the words in the memory in such a way that several words are present in each row. The memory map is thus made more compact. It results in both a row decoder for addressing a row among n locations and a column decoder for addressing a word among m locations in a line of m words of p bits.
Moreover, instead of arranging the row decoder on a memory edge, it has already been suggested to arrange the row decoder in the center of the memory, between two half-planes, symmetrical about the decoder. The memory may even be divided into four planes or more, with several half-decoders.
With regard to the read method, it is generally executed in a differential way. The state of a bit line (that is the lead on which the requested information appears) is determined in comparison with the state of a reference line which behaves like a bit line, whose transmitted information is known. In the case of an EEPROM memory, for example, the requested information is a leakage current, flowing or not flowing in the bit line depending on the information stored in the addressed cell. Such current is compared with a current flowing in the reference line. This differential method permits a fair reliability of the read information.
Moreover, so as to improve the compromise between the access speed and the reliability of a given piece of information, it has also been suggested to carry out the read operation in two phases. In the first phase, the bit line and the reference line are precharged to a potential value, which is intermediate between two possible extreme values, and, in the second phase, the behaviors of the bit line and reference line are compared with one another.
Last, and still with the same object in view, it has been suggested to provide for a balancing phase at the differential amplifier, which is to be used for comparing the behaviors of the bit line and reference line. This balancing phase generally consists in shorting the bit line and the reference line (or the differential amplifier inputs connected to such lines). In this way, the differential amplifier will be able to switch over very quickly to one state or another depending on the read information, irrespective of the state to which it had switched over on the preceding read operation.
In fact, if the amplifier initially kept the state to which it had switched over for the preceding read operation, it would take it a longer time to read a bit having the same value as before than it would take to read a bit having a complementary value, which would be detrimental to the overall operating speed of the memory.
For all of the above reasons, the memories now available may present an organization with n rows of m words of p bits, possibly with a central row decoder, rather than a side decoder, and a read method possibly including precharging and balancing phases.
It is an object of the present invention to further improve the compromises controlling the memory design, and more particularly that of EEPROM memories with plural bit words. Besides the above mentioned compromises regarding reliability and speed, the conventional limitations must be taken into account, such as, for instance, the minimization of the physical area occupied by the memory on an integrated circuit chip.